Mike Bartley
TVS provide specialist test and verification services and products to the worldwide semiconductor and embedded systems industries. TVS is able to deliver start-of-the-art solutions by keeping abreast of latest developments in verification and test through attending, speaking at and organising industry conferences and events, and by writing articles on test and verification methodologies and tools. This channel enables us to share some of this with the community, including presentations from these conferences: DVClub: A special interest group on verification, Formal Verification Conferences, Intelligent Testing, The Multicore Challenge and Verification Futures. Topics includes; Verification, Verification IP (VIP), Requirements Management, Software Testing, Validation, Verification and Test Benchmarking and Outsourcing.

Formal Verification of Security-Properties on RISC-V Processors

Automating Cyber-physical Security Verification in the SoC Design Flow

Improving your VHDL FPGA verification with OSVVM and UVVM

The Era of Agentic Engineering – Roadmap to Level 5

Splitting the die: a modular approach to chiplet design and verification

SRAM: Dead or Alive?

TrIM: An Efficient Systolic Array for Convolutional Neural Networks

Validate and Implement a RISC-V core using AI

Efficiency Improvement and Automation in Design Verification using AI

Case Study on deploying AI in Design Verification for Smarter and Faster Verification of Designs

𝜇CFI: Formal Verification of Microarchitectural Control-flow Integrity

Leveraging FPGA-optimized Equivalence Checking for Security Safetyand Assurance Standards Compliance

Use of Prototyping and Emulation in the semiconductor industry in 2025

HDLRegression: A reliable and efficient tool for FPGA regression testing

Automating the design of bespoke AI accelerators for FPGAs

Pre-silicon Identification of Security Vulnerabilities

Securing Chiplet-Based AI Designs: Enabling End-to-End Protection in Modular Architectures

EEnet verification of a Multilevel DCDC converter IC

Rethinking chip(let) design for next generation ADAS applications

A Real Number Model of a Phased Array Antenna

Digital-Mixed-Signal (DMS) Modelling using Signal Flow

Unify to Verify: A Monorepo Approach for Hardware and Software using Bazel, Cocotb and Verilator

A Novel Security Vulnerability Detection Mechanism Using Information Flow Tracking on a given SOC

How Will AI Change Your Verification Future?

Advanced RISC-V Virtualizer/Hypervisor Verification for CPU & SoC

Bringing CI into Formal Verification

The four horse riders of the silicon apocalypse

Bio-inspired CODECs using steganography

Synergistic stimulus-free verification with next generation static and formal

TechWorks-AI and TAIBOM – Engineering Trustable AI