Synthesis of Digital Systems - IITD

Timing Analysis & Critical Paths

Introduction to Timing Analysis

Multi-level Logic Synthesis: Technology Mapping

Multi-Level Logic Optimisation

Two-level Logic Optimisation

Introduction to Logic Synthesis

Binary Decision Diagrams

Efficient Solution to Retiming & Introduction to Logic Synthesis

Finite State Machine Synthesis: Identifying Common Cubes & Graph Embedding

The Retiming Problem

Finite State Machine Synthesis: Introduction to FSM Encoding

High Level Synthesis and Timing Issues

Force Directed Scheduling & Register Allocation

List Scheduling & Time-constrained Scheduling

Compiler Transformations in High Level Synthesis: Loop Unrolling and Function Inlining

Hardware Transformations & ASAP / ALAP Scheduling

Compiler Transformation in High Level Synthesis: Constant Folding,

Memory Modelling & Compiler Transformation in High Level Synthesis

Language front-end Design Representation

Introduction to High-level Synthesis

VHDL: Specifying Structure, Test Benches, Parameterisation, & Libraries

VHDL: Specifying Hardware Behaviour with Processes

VHDL: Modelling Timing - Events & Transactions

VHDL: Introduction to Hardware Description Languages & VHDL Basics

Chip Design Flow and Hardware Modelling

Outline - What is Synthesis?

Prof. Preeti Ranjan Panda