Dillon Huff

How to Build a Hardware Compiler for Machine Learning and Image Processing Part 3

The Most Important Bit Twiddling Hack for Coding Interviews

How big can deep neural networks get?

How to Build a Hardware Compiler for Machine Learning and Image Processing Part 2

How to Build a Hardware Compiler for Machine Learning and Image Processing Part 1

FCCM Clockwork Presentation 2021

Generating Code from Polyhedral Schedules

Representing Schedules in the Polyhedral Model

What is lexicographic order?

Clockwork: Efficient Static Scheduling for Image Processing Applications on FPGAs (Part 5)

Clockwork: Efficient Static Scheduling for Image Processing Applications on FPGAs (Part 4)

Clockwork: Efficient Static Scheduling for Image Processing Applications on FPGAs (Part 3)

Clockwork: Efficient Static Scheduling for Image Processing Applications on FPGAs (Part 2)

Clockwork: Efficient Static Scheduling for Image Processing Applications on FPGAs (Part 1)

Does dataflow matter for DNN accelerator performance?

How Fast Can Deep Neural Networks Run on FPGAs?

Two Numbers You Should Know Before Designing a Hardware Accelerator

What is the future of computer architecture?

The Polyhedral Model Part 6: Code Generation

The Polyhedral Model Part 5: More on Scheduling

The Polyhedral Model Part 4: Scheduling

The Polyhedral Model Part 3: Integer Linear Programming and Lexicographic Order

The Polyhedral Model Part 2: A Little More Formalism

The Polyhedral Model Part 1: An Intuitive Example

FPGAs vs. GPUs: A Back of the Envelope Analysis

Can FPGAs compete with GPUs in Image Processing? (Part 3) Hardware Compiler Case Studies

Can FPGAs compete with GPUs in Image Processing? (Part 2) Whole Application Case Studies

Can FPGAs compete with GPUs in Image Processing? (Part 1)

Synchronous Data Flow Part 3