Analog Layout & Design

This channel is intended to bridge the gap between new college grads and analog engineering professionals. It will be also useful for analog layout engineers who do not have access to interact with designers.

FinFET transistor

FinFET transistor
LDO Vs BGR

LDO Vs BGR
LDO (регулятор с малым падением напряжения)

LDO (регулятор с малым падением напряжения)
On-Chip Capacitors (MiM, MoM, PiP, Mos Varactor)

On-Chip Capacitors (MiM, MoM, PiP, Mos Varactor)
SPIRAL INDUCTOR [ON-CHIP INDUCTOR]

SPIRAL INDUCTOR [ON-CHIP INDUCTOR]
SERDES LAYOUT (WIRE / INTERCONNECT PARASITICS)

SERDES LAYOUT (WIRE / INTERCONNECT PARASITICS)
BGR (эталон ширины запрещенной зоны)

BGR (эталон ширины запрещенной зоны)
AGND, DGND, ISOLATION (STAR CONNECTION)

AGND, DGND, ISOLATION (STAR CONNECTION)
CTLE (непрерывный линейный эквалайзер): ВЫСОКОСКОРОСТНЫЕ SERDES

CTLE (непрерывный линейный эквалайзер): ВЫСОКОСКОРОСТНЫЕ SERDES
HIGH SPEED SERDES (INTRODUCTION)

HIGH SPEED SERDES (INTRODUCTION)
CURRENT MIRROR ( PART - 1)

CURRENT MIRROR ( PART - 1)
WELL PROXIMITY EFFECT (WPE)

WELL PROXIMITY EFFECT (WPE)
CMOS INVERTER FABRICATION (PART - 3)

CMOS INVERTER FABRICATION (PART - 3)
CMOS FABRICATION PART - 2

CMOS FABRICATION PART - 2
CMOS FABRICATION - PART 1

CMOS FABRICATION - PART 1
FDSOI LATCH UP?

FDSOI LATCH UP?
LATCH UP PREVENTION

LATCH UP PREVENTION
MULTIPLIER & FINGER

MULTIPLIER & FINGER
MOSFET CAPACITANCE

MOSFET CAPACITANCE
ESD (ЧАСТЬ - 4)

ESD (ЧАСТЬ - 4)
ESD (PART - 3)

ESD (PART - 3)
ESD (PART - 2)

ESD (PART - 2)
ESD (Part - 1)

ESD (Part - 1)
CORE & I/O (Voltage Island & Freq Island)

CORE & I/O (Voltage Island & Freq Island)
ЛДМОС

ЛДМОС
GROUND BOUNCE

GROUND BOUNCE
ГЛУБОКАЯ СКВАЖИНА (DNW)

ГЛУБОКАЯ СКВАЖИНА (DNW)
защелка

защелка
resistor divider

resistor divider
Полупроводниковые резисторы часть 2

Полупроводниковые резисторы часть 2