Mike Thompson

double dabble 14bit self check tb

double dabble 14bit self check tb
Verilog Double Dabble

Verilog Double Dabble
WhyDoubleDabbleWorks

WhyDoubleDabbleWorks
DoubleDabble

DoubleDabble
Deep Research Prompt

Deep Research Prompt
AI Hallucinations Document Using Canvas

AI Hallucinations Document Using Canvas
Add sub RTL

Add sub RTL
notebookLM

notebookLM
automated worklogs

automated worklogs
Week 1: To Do

Week 1: To Do
Review of Lab 9 RTL Diagram

Review of Lab 9 RTL Diagram
Zybooks EDAPlayground Workflow

Zybooks EDAPlayground Workflow
State Diagram to Circuit - Shannon Decomposition HW

State Diagram to Circuit - Shannon Decomposition HW
State Diagram to D FF equations HW

State Diagram to D FF equations HW
FF Circuit Analysis (FF to State Diagram) HW

FF Circuit Analysis (FF to State Diagram) HW
FF versus Latch Timing Diagram HW

FF versus Latch Timing Diagram HW
ELC 2337 All NAND Logic Function Implementation

ELC 2337 All NAND Logic Function Implementation
ELC 2337 All NOR Logic Function Realization

ELC 2337 All NOR Logic Function Realization
eda playground file management tip

eda playground file management tip
Top Level Verilog Example

Top Level Verilog Example
lab5 full adder walkthrough revised

lab5 full adder walkthrough revised
ELC 2137 Sprinkler Controller

ELC 2137 Sprinkler Controller
The How and Why of the Dabble part of Double Dabble

The How and Why of the Dabble part of Double Dabble
double dabble examples

double dabble examples
Dabble

Dabble
FSM with Shannon Decomposition

FSM with Shannon Decomposition
Shannon Decomposition - Example 2

Shannon Decomposition - Example 2
Shannon Decomposition - Example 3

Shannon Decomposition - Example 3
Shannon Decomposition - Intro Video

Shannon Decomposition - Intro Video
Three-State Gates

Three-State Gates