First 10 Hours : Digital Logic with Verilog HDL

The easy way to learn VerilogHDL in First 10 Hours aims for education purpose only. It may help in self learning and practicing the basic constructs of VerilogHDL Language for Digital Hardware Modeling. In this learning process we recommend to refer the following wonderful books in order to understand and implement concepts in a meaningful way. This channel can never be a substitute of text book. Therefore, it shall be used as an additional learning resource with other teaching learning methodologies, eg, classroom, laboratory, self reading, and practicing, etc.
We request all viewers and learners to help us in improving the contents by your valuable feedback.
Team: Dr. Neeraj Kr. Shukla, Dr. Charu Rana,Ms. Rakhi Nangia, Ms. Neha Kaushik, Mr. Bhargava Y, Mr. Harsh Gupta, and Ms. Ruby.
Reference Books:
1. Digital Design with an Introduction to the Verilog HDL by M. Morris Mano, 5/e.
2. Verilog Digital System Design by Zainalabedin Navabi, 2/e
3. Verilog Hdl by Samir Palnitkar, 2/e

while Loop in VerilogHDL

while Loop in VerilogHDL
repeat Loop in VerilogHDL

repeat Loop in VerilogHDL
for Loop in VerilogHDL

for Loop in VerilogHDL
Ring Counter in VerilogHDL

Ring Counter in VerilogHDL
MOD 10 or Decade or BCD Up Counter in VerilogHDL

MOD 10 or Decade or BCD Up Counter in VerilogHDL
MOD 5 Up Counter in VerilogHDL

MOD 5 Up Counter in VerilogHDL
Decoder 2 to 4 and Testbench in VerilogHDL

Decoder 2 to 4 and Testbench in VerilogHDL
Synthesizable and Non Synthesizable VerilogHDL Codes

Synthesizable and Non Synthesizable VerilogHDL Codes
Getting Started with Xilinx Vivado using VerilogHDL

Getting Started with Xilinx Vivado using VerilogHDL
Buffer with VerilogHDL in Ubuntu using iVerilog

Buffer with VerilogHDL in Ubuntu using iVerilog
MOD 8 Up Down Counter in Verilog HDL

MOD 8 Up Down Counter in Verilog HDL
MOD 8 Down Counter in Verilog HDL

MOD 8 Down Counter in Verilog HDL
MOD 8 Up Counter in Verilog HDL

MOD 8 Up Counter in Verilog HDL
Blocking and Non blocking Assignment in Verilog HDL

Blocking and Non blocking Assignment in Verilog HDL
D Latch using VerilogHDL in Xilinx Vivado

D Latch using VerilogHDL in Xilinx Vivado
4 to 2 Encoder using VerilogHDL in Xilinx Vivado

4 to 2 Encoder using VerilogHDL in Xilinx Vivado
ModelSim Hello World and NOT Gate in VerilogHDL

ModelSim Hello World and NOT Gate in VerilogHDL
Hold Time Analysis and Simulation using VerilogHDL

Hold Time Analysis and Simulation using VerilogHDL
Setup Time Analysis and Simulation using VerilogHDL

Setup Time Analysis and Simulation using VerilogHDL
Half Subtractor

Half Subtractor
Half Subtractor Testbench

Half Subtractor Testbench
Half Adder Testbench

Half Adder Testbench
Half Adder

Half Adder
Hello World in VerilogHDL

Hello World in VerilogHDL
ISE Design Suite 14.7v - Getting Started for Beginners - How to Work?

ISE Design Suite 14.7v - Getting Started for Beginners - How to Work?
T Flip Flop Testbench

T Flip Flop Testbench
T Flip Flop

T Flip Flop
SR Flip Flop Testbench

SR Flip Flop Testbench
SR Flip Flop

SR Flip Flop
iCARUS Verilog - Installation - Getting Started - Beginner - Hello World

iCARUS Verilog - Installation - Getting Started - Beginner - Hello World