Shrikanth Shirakol

HDL Verilog: Online Lecture 34: Logic Synthesis flow,Examples on extraction of synthesis information

HDL Verilog: Online Lecture 33:Logic Synthesis,Extraction of Synthesis information from verilog code

HDL Verilog: Online Lecture 32: Useful Modelling techniques, conditional compilation, system tasks

HDL Verilog: Online Lecture 30: Functions, Examples: Parity calculation, Left/Right Shifter

HDL Verilog: Online Lecture 31: Task and Function: Factorial, Signed, constant, Recursive function

HDL Verilog: Online Lecture 29: Task and Functions, Verilog code examples using Xilinx simulation

HDL Verilog: Online Lecture 27: Traffic Signal Controller using verilog on Xilinx

HDL Verilog: Online Lecture 28: Revisit to Behavioral modelling, Doubts clarification session

HDL Verilog: Online Lecture 26: Sequential & Parallel blocks, fork and join, Named and Disable block

HDL Verilog: Online Lecture 25: For loop, repeat, forever loops, examples simulation using xilinx

HDL Verilog: Online Lecture 24: Frequency Division, While Loop, Simulation using Xilinx

HDL Verilog: Online Lecture 23: Sequence Counter, Frequency/ Clock divider concept and analysis

HDL Verilog: Online Lecture 22: IA QP discussion, Flipflops, Sequence counters: Ring and Johnson

HDL Verilog: Online Lecture 21:Behavioral style: Counter design, case statement-MUX, Encoder, DEMUX

HDL Verilog: Online Lecture 19:Behavioral style: Condition statement, if else, Flipflops, MUX, etc

HDL Verilog: Online Lecture 18:Behavioral style: Delay based, Event based Timing controls,simulation

HDL Verilog: Online Lecture 17: Behavioral style: Procedural assignments: Blocking and Non blocking

HDL Verilog:Online Lecture 16:Behavioral modelling: Structured Procedures: Initial, always, examples

HDL Verilog:Online Lecture 15:Gatelevel modelling:Mux using buffif, Comparator using full adder code

HDL Verilog:Online Lecture 14:Gatelevel modelling,Gate Delays, Rise,fall,turn off, min/max/typ delay

HDL Verilog:Online Lecture 13:Gatelevel modelling, Gate primitives, Bufif, notif, MUX, 4bit RC adder

HDL Verilog:Online Lecture 12:Dataflow examples with xilinx simulation: MUX, Adders, FF, Counters

HDL Verilog:Online Lecture 11:Dataflow modelling, Operators-II, Operator precedence

HDL Verilog:Online Lecture 10:Unit 2:Dataflow modelling, Expressions, Operands, Operators-I

HDL Verilog:Online Lecture 9:Unit 2:Dataflow modelling,Continuous assignments and delays, simulation

HDL Verilog:Online Lecture 8: Connecting ports by names and order instantiation, Hierarchical names

HDL Verilog:Online Lecture 7 :System task simulations, Modules, ports, port connection rules

HDL Verilog:Online Lecture 6:System task:display,monitor,stop,finish, Comp directives:include,define

HDL Verilog: Online Lecture 5: Vectors, Integers, Real, Time, Arrays, Strings, Parameter, Memories

HDL Verilog: Online Lecture 4: Data types: Registers, Xilinx simulation and stimulus demonstration