deva kumar talluri

mock interview session -2,part-1 by DEV

mock interview session -2,part-2 by DEV

mock interview session -1 by DEV

Class 15@VLSI internship by DEV sir @ AICTE, MSME,APSCHE approved @HMIES

Exam1,part2 answers

2 June 2025

2 June 2025

Class 14@VLSI internship by DEV sir @ AICTE, MSME,APSCHE approved @HMIES

Class 13@VLSI internship by DEV sir @ AICTE, MSME,APSCHE approved @HMIES

Class 12@VLSI internship by DEV sir @ AICTE, MSME,APSCHE approved @HMIES

Axi protocol output wave form explanation

Physical design course demo@Devs institute

Class 11@VLSI internship by DEV sir @ AICTE, MSME,APSCHE approved @HMIES

Class 10@VLSI internship by DEV sir @ AICTE, MSME,APSCHE approved @HMIES

Class 9@VLSI internship by DEV sir @ AICTE, MSME,APSCHE approved @HMIES

Class 8@VLSI internship by DEV sir @ AICTE, MSME,APSCHE approved @HMIES

Class 7@VLSI internship by DEV sir @ AICTE, MSME,APSCHE approved @HMIES

(16-5-25) zero fee high quality VLSI training class -11 by DEV sir

Class 6@VLSI internship by DEV sir @ AICTE, MSME,APSCHE approved @HMIES

(14-5-25) zero fee high quality VLSI training class -10 by DEV sir

System verilog class 8 by DEV sir

Class 5@VLSI internship by DEV sir @ AICTE MSME APSCHE approved @HMIES

Class 4@VLSI internship by DEV sir @ AICTE MSME APSCHE approved @HMIES

(10-5-25) zero fee high quality VLSI training class -9 by DEV sir

System verilog class 7 by DEV sir

Class 1,2,3@VLSI internship by DEV sir @ AICTE MSME APSCHE approved @HMIES

BTech internships training @ MSME, APSCHE, AICTE approved

1port RAM memory(mini project) verilog based design verification(with parameter)

System verilog class 6 by DEV sir

1port RAM memory,TLC (mini projects) verilog based design verification