Kaleidoscope

Design a 2-input XOR using Symbols of 2-input CMOS NAND gate using Cadence Virtuoso

High Skewed , Low-Skewed, and Un-skew CMOS Inverter using Cadence Virtuoso

Design a 2-input NAND Gate using Pseudo-NMOS Logic Families in Cadence Virtuoso

Design and Simulation of a SR Latch using NOR Gates in Cadence Virtuoso

Creating and Simulating a CMOS 2-input NOR Gate using Cadence Virtuoso

2-input Domino AND Gate Design using Cadence Virtuoso

6T SRAM Design with Inverter Symbol Creation using Cadence Virtuoso: DC Simulation

Creating and Simulating a CMOS 2-input NAND gate using Cadence Virtuoso

Common Source Amplifier using Cadence Virtuoso: DC Response, Transient Response, and AC Response

CMOS Inverter using Cadence Virtuoso – Part 4: Delay Estimation

CMOS Inverter using Cadence Virtuoso – Part 3: Layout, DRC, LVS, and RC Extraction

CMOS Inverter using Cadence Virtuoso – Part 2: Symbol Creation after Schematic Design and Simulation

CMOS Inverter using Cadence Virtuoso – Part 1: Schematic Design and Simulation

MOSFET's Short Channel Effect using Cadence Virtuoso: DIBL (Drain-Induced Barrier Lowering)

MOSFET's Short Channel Effect using Cadence Virtuoso: Threshold Voltage (Vt) roll-off

MOSFET's Current vs Voltage Characteristics using Cadence Virtuoso: Part 2

MOSFET's Current vs Voltage Characteristics using Cadence Virtuoso: Part1