SoC & FPGA

FPGA Setup and Hold Violation Analysis and Mitigation

FPGA Setup and Hold Violation Analysis and Mitigation
Глубокое погружение в адаптивную систему-на-модулях Kria AMD Xilinx

Глубокое погружение в адаптивную систему-на-модулях Kria AMD Xilinx
Передовые методологии проектирования для AMD Xilinx Versal Network on Chip (NoC)

Передовые методологии проектирования для AMD Xilinx Versal Network on Chip (NoC)
NoC Design for Experts and Beginners : When to Use IPI or Modular Flows

NoC Design for Experts and Beginners : When to Use IPI or Modular Flows
The AMD Xilinx Modular Network on Chip NoC Design Process : An In Depth Analysis

The AMD Xilinx Modular Network on Chip NoC Design Process : An In Depth Analysis
Комплексный анализ корпусов DDR SDRAM UDIMM, SODIMM, RDIMM и LRDIMM

Комплексный анализ корпусов DDR SDRAM UDIMM, SODIMM, RDIMM и LRDIMM
The AMD Versal™ Modular Network on Chip A Deep Dive into RTL Design with Parameterized Macros XPMs

The AMD Versal™ Modular Network on Chip A Deep Dive into RTL Design with Parameterized Macros XPMs
Vivado vs Quartus vs Libero vs Radiant – Strengths, weaknesses, and quirks of vendor toolchains

Vivado vs Quartus vs Libero vs Radiant – Strengths, weaknesses, and quirks of vendor toolchains
Open Source FPGA Movement – Yosys, nextpnr, LiteX, OpenTitan

Open Source FPGA Movement – Yosys, nextpnr, LiteX, OpenTitan
FPGA as a Service – AWS F1, Azure NP series, and the cloud’s role in FPGA adoption

FPGA as a Service – AWS F1, Azure NP series, and the cloud’s role in FPGA adoption
Versal ACAP и адаптивные SoC — что на самом деле означает «за пределами FPGA»

Versal ACAP и адаптивные SoC — что на самом деле означает «за пределами FPGA»
ПЛИС в центрах обработки данных — реальные истории внедрения от гипермасштабируемых компаний

ПЛИС в центрах обработки данных — реальные истории внедрения от гипермасштабируемых компаний
Career Paths in FPGA Engineering – Skills in demand, how to grow, and what’s next

Career Paths in FPGA Engineering – Skills in demand, how to grow, and what’s next
The Future of Programmable Logic – Will FPGAs remain niche, or become mainstream compute

The Future of Programmable Logic – Will FPGAs remain niche, or become mainstream compute
The Road to Chiplets & Heterogeneous Integration – FPGAs as part of multi die systems

The Road to Chiplets & Heterogeneous Integration – FPGAs as part of multi die systems
Out of Order Transactions in AXI protocol – How IDs and reordering improve performance

Out of Order Transactions in AXI protocol – How IDs and reordering improve performance
The AXI Family Tree – AXI3, AXI4, AXI4 Lite, and AXI4 Stream

The AXI Family Tree – AXI3, AXI4, AXI4 Lite, and AXI4 Stream
Common AXI Design Pitfalls – Deadlocks, starvation, and throughput bottlenecks

Common AXI Design Pitfalls – Deadlocks, starvation, and throughput bottlenecks
AXI4 Stream in High Speed Data Applications – Video processing, networking, and DSP pipelines

AXI4 Stream in High Speed Data Applications – Video processing, networking, and DSP pipelines
Handshake Signals Explained in AXI Protocol – VALID, READY, and how backpressure works

Handshake Signals Explained in AXI Protocol – VALID, READY, and how backpressure works
AXI in FPGA Development – Integrating IP cores via AXI

AXI in FPGA Development – Integrating IP cores via AXI
Когда AXI — не лучший выбор. Случаи, когда лучше использовать более простые или индивидуальные ав...

Когда AXI — не лучший выбор. Случаи, когда лучше использовать более простые или индивидуальные ав...
Отладка кошмара AXI

Отладка кошмара AXI
Breaking Down the 5 AXI Channels–Read Address, Read Data, Write Address, Write Data, Write Response

Breaking Down the 5 AXI Channels–Read Address, Read Data, Write Address, Write Data, Write Response
AXI Bursts Demystified – Fixed, incrementing, and wrapping bursts with real examples

AXI Bursts Demystified – Fixed, incrementing, and wrapping bursts with real examples
What is AXI and Why It Matters?

What is AXI and Why It Matters?
Memory Hierarchy Design for SoC (Part 1)

Memory Hierarchy Design for SoC (Part 1)
Memory Hierarchy Design for SoC (Part 2)

Memory Hierarchy Design for SoC (Part 2)
FPGA vs ASIC vs SoC – What’s the Difference?

FPGA vs ASIC vs SoC – What’s the Difference?
System on Chip (SoC) Design Flow Explained

System on Chip (SoC) Design Flow Explained