RTL Engineering

Educational videos covering various topics in computer engineering and computer architecture, specifically focusing on mid 1990s to early 2000s computers and game consoles. Most topics will be presented with FPGA implementation in mind. These topics will be presented assuming some prior knowledge of computer systems and digital electronics.

GPU Memory, and Clogged Pipes (Part 3 - PS2 and Dreamcast/PowerVR) - #GPUJune2

GPU Memory, and Clogged Pipes (Part 3 - PS2 and Dreamcast/PowerVR) - #GPUJune2
GPU Memory, and Clogged Pipes (Part 2 - 3dfx Voodoo) - #GPUJune2

GPU Memory, and Clogged Pipes (Part 2 - 3dfx Voodoo) - #GPUJune2
GPU Memory, and Clogged Pipes (Part 1 - PS1 and N64) - #GPUJune2

GPU Memory, and Clogged Pipes (Part 1 - PS1 and N64) - #GPUJune2
GPUs, Points, and Lines - #GPUJune2

GPUs, Points, and Lines - #GPUJune2
Pentium MMX Predecoding in a FPGA

Pentium MMX Predecoding in a FPGA
Quake, Floating Point, and the Intel Pentium

Quake, Floating Point, and the Intel Pentium
MicroOps in the Pentium MMX

MicroOps in the Pentium MMX
x86 Decoding Simulation in the Pentium MMX

x86 Decoding Simulation in the Pentium MMX
x86 Front End Complexity (Part 2 - Pentium MMX)

x86 Front End Complexity (Part 2 - Pentium MMX)
x86 Decoding Simulation in the 486

x86 Decoding Simulation in the 486
x86 Decoding Simulation in the Pentium P5

x86 Decoding Simulation in the Pentium P5
x86 Front End Complexity (Part 1 - Pentium P5)

x86 Front End Complexity (Part 1 - Pentium P5)
Channel Update, New Workflow, and Project Teaser

Channel Update, New Workflow, and Project Teaser
Implementation of a VR4300 ALU Shifter

Implementation of a VR4300 ALU Shifter
A High Performance FPGA Game Console Platform

A High Performance FPGA Game Console Platform
Implementation of an Efficient Floating-Point Complementor

Implementation of an Efficient Floating-Point Complementor
Analysis of a Tensor Core

Analysis of a Tensor Core
Implementing an Efficient MIPS III Multi-Cycle Multiplier

Implementing an Efficient MIPS III Multi-Cycle Multiplier
Designing an Efficient MIPS III Load Store Unit

Designing an Efficient MIPS III Load Store Unit
Designing an Efficient MIPS TLB [Part 2]

Designing an Efficient MIPS TLB [Part 2]
Designing an Efficient MIPS TLB [Part 1]

Designing an Efficient MIPS TLB [Part 1]
Designing an Efficient Combined Register File

Designing an Efficient Combined Register File
VR4300 Primer

VR4300 Primer
Designing an Efficient Leading Zero Counter

Designing an Efficient Leading Zero Counter
N64 Hardware Architecture

N64 Hardware Architecture
Game Console Hardware Architecture (5th and 6th Generation)

Game Console Hardware Architecture (5th and 6th Generation)
FPGA Game Console Emulation and its Limitations

FPGA Game Console Emulation and its Limitations