Observe and Regulate Memory Interference on MPSoC: a Practical Approach Presented by Andrea Bastoni
wolfSSL solutions for the AMD/Xilinx UltraScale+ MPSoC and Versal
RDMA enabled NIC on the iWave Zynq™ UltraScale+™ MPSoC Development kit Powered by AMD
Zynq Standalone Ethernet: Data Exchange with Python Scripts
Ultra96 (Xilinx UltraScale+ MPSoC) Hands-on Experience Lecture #1 (Turkish)
Añadir LED Heartbeat a Linux en Zynq MPSOC
Ejecutar Linux en Zynq MPSOC parte 2
Ejecutar Linux en Zynq MPSOC parte 1
Using the Adaptive SoC TRDs to Test Custom Image Recognition Tasks
Implementing and Optimizing MIO on AMD’s Zynq™ UltraScale+™ MPSoC and RFSoC Platforms
Single Event Effects Assessment of UltraScale+ MPSoC Systems Under Atmospheric Radiation
Best Practices for FPGA and Software Integration in MPSoC Architectures
ALINX AXU2CG-E: Unleashing the Power of Xilinx Zynq UltraScale+ MPSoC
Hardware Software Codesign for Embedded AI - Lecture 11 - Design Tools and Methods for Zynq MPSoC
Hardware Software Codesign for Embedded AI - Lecture 10 - Overview of Zynq MPSoC Architecture - II
Hardware Software Codesign for Embedded AI - Lecture 9 - Overview of Zynq MPSoC Architecture - I
Hardware Software Codesign for Embedded AI - Lecture 8 - FPGA vs Zynq vs Zynq MPSoC
Graph Convolutional Neural Networks for Event Based Vision for AMD SoC FPGA (Team AOHW-284) #AOHW
Overview of Zynq® UltraScale+™ ZU19/ZU17/ZU11 MPSoC Powered SoM and Development kit #iwave
New XMC Module has Zynq UltraScale+ MPSoC for Embedded I/O Processing & Programmable Logic Functions