Simple UVM Testbench, from Spec to Testbench (ALU Verification with UVM)

A simple Universal Verification Methodology based testbench for learning purposes.

ALU SPEC:
https://drive.google.com/file/d/1wm3q...

Testbench Architecture Blockdiagram:
https://drive.google.com/file/d/1wXIE...

EDA Playground Code:
https://www.edaplayground.com/x/PtRg

GitHub Code: (Same code as in EDA Playground)
https://github.com/Psichico/Universal...


Helpful links:

1. UVM Config DB:
https://www.synopsys.com/content/dam/...

2. UVM Verbosity:
http://cluelogic.com/2015/05/uvm-tuto...

0:00 Start
2:41 Top Module
10:06 Interface
16:37 Test Class
25:35 Other Components
31:20 Sequence Item
34:45 Sequence
37:52 Bringing it together
1:09:51 Driver Run_Phase
1:14:49 Monitor Run_Phase
1:22:19 Scoreboard Class


Contact Me:
Linkedin:
  / jaimil-patel