Structural style of modelling in VHDL
Автор: Shubham N Gour
Загружено: 2019-06-25
Просмотров: 3253
In structural style of modelling, an entity is described as a set of interconnected components.
The top-level design entity’s architecture describes the interconnection of lower-level design entities. Each lower-level design entity can, in turn, be described as an interconnection of design entities at the next-lower level, and so on.
Structural style is most useful and efficient when a complex system is described as an interconnection of moderately complex design entities. This approach allows each design entity to be independently designed and verified before being used in the higher-level description.
Other videos link
1.Introduction to VHDL
• Introduction to VHDL
2.design units and entity description
• Design units of VHDL and entity definition
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