RTL2GDS Demo Part 4.1: Place and Route - Getting Started

Digital VLSI Design - Hands on Demonstration

This is part 4 of a series of demonstrations for carrying out an RTL2GDS ASIC Digital Implementation Flow. In this series, I cover the entire flow, starting with simulation and direct test of an RTL block, through synthesis, floorplanning, placement and routing. The flow is demonstrated on a small toy counter block that I showed in my Digital VLSI Design (DVD) lecture series and goes through all steps of the digital design flow. In this series, we use Cadence tools: Xcelium, Genus, Innovus, Voltus and Tempus and work according to the methodology that I developed for the EnICS Labs at Bar-Ilan University.

In this video, I run place and route (PNR) on the post-synthesis netlist of the toy counter block using the results we got from Part 2 of this series (   • RTL2GDS Demo Part 2.2: Synthesis with Genus  ). The entire flow is carried out in Cadence Innovus. The video is divided into 9 sections, as follows:
RTL2GDS Demo Part 4.1: Place and Route - Getting Started (   • RTL2GDS Demo Part 4.1: Place and Route - G...  )
RTL2GDS Demo Part 4.2: Place and Route - Init Design (   • RTL2GDS Demo Part 4.2: Place and Route - I...  )
RTL2GDS Demo Part 4.3: Place and Route - Global Nets (   • RTL2GDS Demo Part 4.3: Place and Route - G...  )
RTL2GDS Demo Part 4.4: Place and Route - Specify Floorplan (   • RTL2GDS Demo Part 4.4: Place and Route - S...  )
RTL2GDS Demo Part 4.5: Place and Route - Rings and Physical Cells (   • RTL2GDS Demo Part 4.5: Place and Route - R...  )
RTL2GDS Demo Part 4.6: Place and Route - Power Grid (   • RTL2GDS Demo Part 4.6: Place and Route - P...  )
RTL2GDS Demo Part 4.7: Place and Route - Placement (   • RTL2GDS Demo Part 4.7: Place and Route - P...  )
RTL2GDS Demo Part 4.8: Place and Route - CTS (   • RTL2GDS Demo Part 4.8: Place and Route - CTS  )
RTL2GDS Demo Part 4.9: Place and Route - Routing and Signoff (   • RTL2GDS Demo Part 4.9: Place and Route - S...  )

This demonstration is very simplistic, as the toy counter block is tiny. However, this first introduction to the physical design flow shows the mandatory steps and the basic commands, which I believe provides a more smooth entrance into this complex process. Part 5 of this series revisits the entire RTL2GDS flow on a larger, full-chip example, including SRAM blocks and I/Os to provide a more complete demonstration.

The skeleton template of the scripts used in this tutorial can be found on the EnICS Labs github at https://github.com/enics-labs/rtl2gds...
Feel free to clone the repo and send comments and suggestions for improvement.

The entire DVD course can be accessed at https://enicslabs.com/academic-course...
You can find slide decks and links to all of my lectures on the EnICS Labs website at https://enicslabs.com/education/ or directly access my recordings through my YouTube channel @aditeman

Note that I have made significant effort to blur and block any and every reference of external IP, beyond the basic features of the EDA tools and open source projects. If you notice any piece of information that is not blocked, please inform me at [email protected] and I will correct this as soon as possible.



All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University