Lessons learned while formally verifying the ZipCPU - Dan Gisselquist - ORConf 2018
Автор: FOSSi Foundation
Загружено: 2018-11-07
Просмотров: 3890
The ZipCPU is a three-year old CPU and ISA designed for low logic FPGA's. One of the challenges of any CPU design, to include the ZipCPU, is coming up with a sufficiently robust test suite to exercise all of the possible logic flows within the CPU. While formal methods can be used for this task, they are traditionally viewed as too computationally expensive to formally verify something as complex as a CPU.
Contrary to this view, the ZipCPU has now been formally verified using SymbiYosys. As a result, many bugs have been found and fixed--bugs not found previously using canned test cases. Not only that, it has also become easier to modify the CPU as necessary to achieve lower logic utilization, knowing that the formal solver will find any bugs in the updated implementations.
Presenter: Dan Gisselquist
Dr. Gisselquist is the owner of Gisselquist Technology, LLC, a services based microbusiness focused on providing superior computer engineering and signal processing services to our customers. Dr. Gisselquist has an M.D. in Computer Engineering and a Ph.D. in Electrical Engineering both from the U.S. Air Force Institute of Technology. His current work is focused on the ZipCPU, the environment, tool-suite, and peripherals necessary to support both it and any customer applications. He is also known for the ZipCPU blog, and has recently taken up training others in formal methods.
Talk recorded at ORConf 2018, the Open Source Digital Design conference, held in Gdansk, Poland and organized by the FOSSi Foundation.
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