FPGA Hardware-Accelerated LLVM-to-RISC-V Just-In-Time Compiler

The Dynamic Compiler is a hardware-accelerated Just-In-Time (JIT) compiler implemented on an FPGA, designed to optimize runtime instruction execution for RISC-V. Unlike traditional software JIT compilers, our approach accelerates execution by dynamically translating and scheduling instructions at the hardware level, improving performance, security, and power efficiency.

This project enhances digital by providing low-latency, energy-efficient computing for edge devices, AI accelerators, and embedded systems. By offloading critical compilation and optimization tasks to hardware, we mitigate security risks such as code injection and reverse engineering, making it ideal for applications in secure computing, cloud infrastructure, and high-performance embedded systems.

With its entrepreneurial potential, this project supports UNSDG Goal 9 (Industry, Innovation, and Infrastructure) by advancing scalable, sustainable computing solutions that bridge the gap between software flexibility and hardware performance.