What is inside a computer microchip?

Chips are making a huge impact on all our lives. Mobile phones, laptops, smart watches, smart cars. Chips Everywhere. So, how are chips produced? Simply, it requires two stages: chip design and chip manufacturing. The design stage is to design the logical and physical structure of the chip, while the manufacturing stage is to create the actually usable chip according to the design plans. We will introduce the technologies used in the chip design stage.

Chips are like digital brains. All data in the chip is represented in binary form. The numbers 1 and 0 are represented by the on and off states of the circuit. All the operations performed in the chip are realized by a structure called "logic gates." There are many types of "logic gates." For example, the "and gate" has two inputs and one output. The output is 1 only if all inputs are 1; otherwise, the output is 0. Like this circuit, the light is on only when both switches are on. When only one switch or neither is on, the light goes off. "AND", "OR", and "NOT gate" are the most basic logic gates. The "truth table" can record the inputs and outputs of the logic gates. Different logic gates can be represented by specific symbols. The logic gates that implement a sub-task are packaged into separate modules for easy reuse, called "macros." Wires are used to connect many macros with different roles on a chip.

Placing these macros in a suitable position to achieve the best chip performance is a key challenge in chip design, also called the placement problem. The placement problem is very difficult because the search space grows exponentially with range. The state space of the Go game is about 361 powers of 3. However, the possible placement plans can be over 10 to the 2500th power! We cannot use a simple brute-force method. How do you score a placement plan? Experts score in three aspects: wirelength, congestion, and overlap.

The wirelength is the total length of the wires. For the following two plans, which one is better? The answer is the right one: the shorter the wirelength, the better, because there is a time delay in the propagation of signals on the wires. Shorter wires allow information to travel faster, thus increasing the speed of chips. Long wires can slow down the device. The second aspect is congestion, which is the crowding of the macros. For the following two plans, which is better? The answer is right because the macros cannot be placed too crowded. An overcrowded placement will lead to heat dissipation problems and block information transmission. If congestion is not handled correctly, the device can heat up quickly. The last aspect is overlap. For the following two plans, which one is better? The answer is still the right one because the macros cannot overlap each other. It is a design rule based on chip manufacturing. If macros overlap, the chip will not meet the manufacturing requirements and cannot work properly.

The placement problem is also an algorithm design problem. The inputs are macro sizes and connectivity relationships; the output is the optimum placement solution. It has been studied for more than 60 years.
We use advanced AI algorithms to find the best solution for the placement problem.

Our first version method, MaskPlace, which solves the visual representation problem of macros. It generates three feature matrices: position, wire, and view to represent the placement state. MaskPlace is an online method and has limitations. So, we propose our second method, ChipFormer. We collected existing placement data for pre-training. Also, we use a graph-variant self-encoder to extract the connectivity structure features of the macros. Our method is trained on the transformer model to predict the next placement actions. As a result, ChipFormer can learn from existing placement experience while improving its effectiveness and speed. ChipFormer can reduce wire length by 60-90%, congestion by 50-80%, and maintain 0 overlap between macros while improving placement speed by 10 times.

According to Moore's Law, the number of gates on a chip doubles every two years. Therefore, there is still a big challenge to efficiently perform the placement of massively integrated chips. We will continue to improve our method to enable the chip placement with more macros.

At the same time, 2D chips are gradually developing into 3D chips. How to effectively generate the placement of 3D chips is also one of the directions we will explore. As we approach the physical limits of the microscopic, researchers are also looking for new ways to improve the chip's performance. The main directions include 3D chip stacking, new materials, neuromorphic computing, quantum computing, and optical computing. With the limits of Moore's Law gradually approaching, the future of chips will involve a combination of these approaches while relying on continuous optimization and innovation in hardware and software.