PS PL BRAM Data Interaction
Автор: Atefeh Salimi
Загружено: 2025-12-01
Просмотров: 546
In this video, we explore how the Processing System (PS) and Programmable Logic (PL) interact through Block RAM (BRAM) on the Zybo Z7 / Zynq-7000 platform. You’ll learn the complete workflow—from hardware design in Vivado to software access in SDK/Vitis.
We cover:
🔹 Understanding the PS–PL memory architecture on Zynq
🔹 Creating and configuring BRAM using the AXI BRAM Controller
🔹 Connecting custom logic (Verilog/VHDL) to BRAM in the PL
🔹 Mapping BRAM into the ARM processor's address space
🔹 Writing and reading BRAM data from the PS
🔹 Debugging techniques and common pitfalls
This tutorial is ideal for FPGA developers, embedded engineers, and students working with Zynq SoCs, AXI interfaces, and memory-mapped hardware acceleration.
Whether you are building a custom accelerator, testing data transfer, or learning Zynq fundamentals, this step-by-step guide will help you confidently implement BRAM communication between the PL and PS.
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