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Delivering 224G SerDes with a path to 448G to address AI ML bandwidth demand Presented by C
Автор: Open Compute Project
Загружено: 2024-10-21
Просмотров: 2334
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"Naim Ben-Hamida (Senior Director Of Analog Asic) - Ciena
Ciena‚as unmatched expertise in delivering high-speed interconnect solutions has led to the successful introduction of the industry‚as 1st 3nm DSP ASIC and single carrier 1.6Tb/s coherent solution to market. In this session- Ciena provides details around its 3nm-based 224G SerDes and insights into performance that can be achieved. Key driving factor in enabling 448G SerDes is the need for higher analog bandwidth components- which will also be covered in this session- and supported by a proof-of-concept demo."
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