RISC-V Assembly Code #4: Asm Directives, Pseudo Instructions
Автор: hhp3
Загружено: 2024-10-17
Просмотров: 4492
A multipart series describing the RISC-V core (RV32, RV64) and its assembly language. We describe the ISA, registers, and instructions and cover some optional extensions.
This episode describes the pseudo instructions and assembler directives. We also discuss the linking process.
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