SystemVerilog RNM programming tutorial: Signal-flow vs Structural DAC model

In this video I further expand on the topic of modeling a simple DAC. To better assess how good/bad original model is, I introduce a new model here which is based on a concept of a structural electrical modeling in SystemVerilog, when a set of analog primitives like capacitors, inductors, resistors, switches etc can be used to model analog circuits. I explore what are the differences between a simple signal-flow model and what are the benefits of a structural DAC model. In this case, I use a simple model of a voltage-mode non-inverting R2R DAC.
For better context, please check previous videos in this playlist.