[FPGA 2022] RapidStream: Parallel Physical Implementation of FPGA HLS Designs ✨

Pongstorn Maidee, Xilinx, Inc.
Yun Zhou, Ghent University
Chris Lavin, Xilinx, Inc.
Jie Wang, University of California, Los Angeles
Yuze Chi, University of California, Los Angeles
Weikang Qiao, University of California, Los Angeles
Alireza Kaviani, Xilinx, Inc.
Zhiru Zhang, Cornell University
Jason Cong

FPGAs require a much longer compilation cycle than conventional computing platforms like CPUs. In this paper, we shorten the overall compilation time by co-optimizing the HLS compilation (C-to-RTL) and the back-end physical implementation (RTL-to-bitstream). We propose a split compilation approach based on the pipelining flexibility at the HLS level, which allows us to partition designs for parallel placement and routing then stitch the separate partitions together. We outline a number of technical challenges and address them by breaking the conventional boundaries between different stages of the traditional FPGA tool flow and reorganizing them to achieve a fast end-to-end compilation.Our research produces RapidStream, a parallelized and physical-integrated compilation framework that takes in an HLS dataflow program in C/C++ and generates a fully placed and routed implementation. When tested on the Xilinx U250 FPGA with a set of realistic HLS designs, RapidStream achieves a 5-7× reduction in compile time and up to 1.3× increase in frequency when compared to a commercial-off-the-shelf toolchain. In addition, we provide preliminary results using a customized open-source router to reduce the compile time up to an order of magnitude in the cases with lower performance requirements. The tool is open-sourced at github.com/Licheng-Guo/RapidStream.

ACM Digital Library: https://dl.acm.org/doi/10.1145/349042...



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