UART VHDL implementation in FPGA and data exchange with host PC

Implement a UART communication protocol using VHDL on an FPGA development board.
The video covers both theoretical concepts and practical implementation using Xilinx Vivado.
Key Topics Covered:
• UART protocol fundamentals including frame structure, start/stop bits, and asynchronous communication
• VHDL module implementation for both transmitter (TX) and receiver (RX) sections
• Parallel-to-serial and serial-to-parallel data conversion concepts
• Baud rate calculations and timing considerations (115,200 bps example)
• USB-to-UART bridge interfacing for modern PC connectivity
Practical Implementation:
• Complete Vivado project setup for Artix-7 AC701 evaluation board
• Block design creation with clocking wizard and system reset configuration
• Pin assignment and constraints file generation
• Two operational modes demonstrated:
1. Loopback Mode: Testing UART functionality by echoing received data
2. Data Generation Mode: Transmitting custom strings and sine wave data from FPGA to PC
Hardware Setup:
• AC701 FPGA evaluation board with 200MHz system clock
• USB-to-UART bridge connection (pins T19/U19)
• Serial terminal communication at 115,200 baud rate
Software Tools:
• Xilinx Vivado for FPGA design and implementation
• Integrated Logic Analyzer (ILA) for signal debugging
• TeraTerm for basic serial communication
• Custom Python GUI application for advanced data visualization and plotting

Git Repositories:
https://github.com/jakubcabal/uart-fo...
https://github.com/FPGAPS/uart-for-fpga

Time Index:
00:00 Introduction to UART
06:35 Start Vivado design of UART VHDL module
07:28 UART module in loop back mode
12:08 I/O planning and FPGA Pin assignment
13:41 UART hello world transmission with Tera Term
15:54 UART module in data exchange mode
18:02 UART Sine data exchange with python script