RTL2GDS Demo Part 5.2: SoC Demo - Running Compilation

Digital VLSI Design - Hands on Demonstration

This is part 5 of a series of demonstrations for carrying out an RTL2GDS ASIC Digital Implementation Flow.

In the fifth part of the series, I move on from a small RTL block to a full-fledged (albeit, very simple) System-on-Chip, including instantiated SRAM blocks and IOs. This full chip demo covers the entire flow, starting with an overview of the design, demonstration of running a C program on the SoC, through synthesis, Full-Chip floorplanning, placement, routing, and fixing DRCs on the post-route design. In this series, we use Cadence tools: Xcelium, Genus, Innovus, Voltus and Tempus and work according to the methodology that I developed for the EnICS Labs at Bar-Ilan University.

This final part of the series demonstrates all of the stages of the flow on the SoC, based on the RI5CY core from the PULP Project at ETH-Zurich (https://pulp-platform.org/). This extensive series of videos is broken up into eight sections:
RTL2GDS Demo Part 5.1: SoC Demo - SoC Overview (   • RTL2GDS Demo Part 5.1: SoC Demo - SoC Over...  )
RTL2GDS Demo Part 5.2: SoC Demo - Running Compilation (   • RTL2GDS Demo Part 5.2: SoC Demo - Running ...  )
RTL2GDS Demo Part 5.3: SoC Demo - SoC Synthesis (   • RTL2GDS Demo Part 5.3: SoC Demo - SoC Synt...  )
RTL2GDS Demo Part 5.4: SoC Demo - Moving on to Innovus (coming soon!)
RTL2GDS Demo Part 5.5: SoC Demo - Full Chip Floorplan (coming soon!)
RTL2GDS Demo Part 5.6: SoC Demo - SoC Placement (coming soon!)
RTL2GDS Demo Part 5.7: SoC Demo - Clock Tree Synthesis (coming soon!)
RTL2GDS Demo Part 5.8: SoC Demo - SoC Routing and Chip Finishing (coming soon!)


The skeleton template of the scripts used in this tutorial can be found on the EnICS Labs github at https://github.com/enics-labs/rtl2gds...
Feel free to clone the repo and send comments and suggestions for improvement.

The entire DVD course can be accessed at https://enicslabs.com/academic-course...
You can find slide decks and links to all of my lectures on the EnICS Labs website at https://enicslabs.com/education/ or directly access my recordings through my YouTube channel @aditeman

Note that I have made significant effort to blur and block any and every reference of external IP, beyond the basic features of the EDA tools and open source projects. If you notice any piece of information that is not blocked, please inform me at [email protected] and I will correct this as soon as possible.


All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University
https://enicslabs.com/