ZK12: X-check: A Native Binary Tower Field ISA Design - Radi Cojbasic

This was recorded at the ZK12 - Zero Knowledge Summit 12 on October 8th, 2024 in Lisbon, Portugal.

https://www.zksummit.com/

Title: X-check: A Native Binary Tower Field ISA Design
Speaker: Radi Cojbasic
Project: Irreducible

Description:
CPU proof generation bottlenecks are typically tackled by GPU- and FPGA-based hardware acceleration. Time-consuming SW processes, e.g. NTT, are replaced with custom, tailor-made HW modules. While effective, this approach lacks flexibility - HW modules serve a single purpose, and SW/HW integration efforts are rarely reusable. This is the premiere of a novel approach to ZKP computing which achieves the industry's highest level of SW/HW co-design. To accelerate Binius, we designed a new compiler, ISA and 16-core CPU that operates over the Binary Tower fields. Unlike bespoke HW accelerators, this approach enables moving the entire proof generation to the X-check-based multi-core System-on-Chip. We have successfully demonstrated this design on FPGA and achieved a 10x speed-up for the Keccak benchmark, compared to the reference x86 implementation. This acceleration method allows frequent algorithmic and SW changes, while running on the same HW, achieving the same flexibility of the CPU proof generation.

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