RTL2GDS Demo Part 3.2: Gate-level Simulation

Digital VLSI Design - Hands on Demonstration

This is part 3 of a series of demonstrations for carrying out an RTL2GDS ASIC Digital Implementation Flow. In this series, I cover the entire flow, starting with simulation and direct test of an RTL block, through synthesis, floorplanning, placement and routing. The flow is demonstrated on a small toy counter block that I showed in my Digital VLSI Design (DVD) lecture series and goes through all steps of the digital design flow. In this series, we use Cadence tools: Xcelium, Genus, Innovus, Voltus and Tempus and work according to the methodology that I developed for the EnICS Labs at Bar-Ilan University.

In the first half of this demo (   • RTL2GDS Demo Part 3.1: Gate-level Simulati...  ), I ran gate-level simulation (GLS) on the post-synthesis netlist of the toy counter block, using the same testbench that we ran on the RTL in Part 1 of the series (   • RTL2GDS Demo Part 1: Logic Simulation with...  ). The initial GLS was run with the zero-delay model to demonstrate equivalence between RTL and gate-level designs (under the same stimuli). After this, timing back-annotation (SDF backannotation) was applied to provide delays within the simulation.
In this half of the demo, I show how during the SDF backannotated simulation, we write out an activity file (VCD, TCF) and use this for accurate power estimation within Cadence Voltus. We then go over the power consumption reports provided by this estimation.

The skeleton template of the scripts used in this tutorial can be found on the EnICS Labs github at https://github.com/enics-labs/rtl2gds...
Feel free to clone the repo and send comments and suggestions for improvement.

The entire DVD course can be accessed at https://enicslabs.com/academic-course...
You can find slide decks and links to all of my lectures on the EnICS Labs website at https://enicslabs.com/education/ or directly access my recordings through my YouTube channel @aditeman

Note that I have made significant effort to blur and block any and every reference of external IP, beyond the basic features of the EDA tools and open source projects. If you notice any piece of information that is not blocked, please inform me at [email protected] and I will correct this as soon as possible.



All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University