Panel-Level Packaging Forum: Key Metallization Technologies

As AI and high-performance computing (HPC) demand surges, advanced wafer-level packaging faces capacity shortages. Panel-level packaging (PLP) improves efficiency by shifting from round to square substrates, allowing more chips per panel, reducing material waste, and lowering costs. With up to 95% utilization, PLP offers higher I/O, smaller size, better performance, and lower power consumption.
However, challenges remain, requiring collaboration across the supply chain. This forum on PLP Metallization Technologies will explore sputtering, plating, process integration, and materials with insights from five leading global companies, helping participants stay ahead of industry trends and seize new opportunities.

📍 TGV Metallization : Trends and Innovations- PC Liu ,General Manager(UVAT Technology Co., Ltd)
📍 Panel Level Packaging: Roadmap and Key Solutions- Brian Gokey ,Director–IC Substrate(MacDermid Alpha)
📍 Advancements in Panel-Level Sputtering: RDL Seed Layer Deposition, Thermal Interface Metallization, and Seed Layer Processes for Vertical Interconnects (Glass Substrates/Interposer TGVs)- Dr. Stanley Low, Product Marketing Manager(Evatec AG)
📍 Metal oxide seed layer for Eless copper plating on glass interposer and substrate- Roger Liu, Assistant Manager(TAIWAN UYEMURA CO., LTD)
📍 Advanced Dry Process Technologies needed to Enable Substrate Scaling- Harish Penmethsa, Deputy General Manager(Applied Materials, Inc.)