Verilog HDL Tutorial Part 11 | Negative Numbers in Verilog | Signed vs Unsigned, Two’s Complement

Welcome to AK APT LOGICS – Verilog HDL Tutorial Series 🎥

In this Part 11, we explain how Negative Numbers are represented in Verilog HDL using two’s complement. We also discuss how different data types (reg, reg signed, and integer) handle negative values.

📖 Topics Covered

Syntax: - [size]'[base][number]

Illegal forms like 8'd-4

Two’s complement representation of negatives

Unsigned reg vs reg signed vs integer

Difference in displayed results depending on data type

Rules for using signed modifier (after the data type only)

📌 Example Code
module neg_number;
integer a, b;
initial begin
a = -6'd3; // Unsigned reg → 61 if stored as reg, -3 if integer
b = -6'sd9; // Signed → -9
$display("a = %0d b = %0d", a, b);
$display("a = %0b b = %0b", a, b);
end
endmodule

📌 Output
a = -3 b = -9
a = 111101 b = 110111


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