Verilog HDL Tutorial Part 19 | Time and Realtime Data Types in Verilog | 64-bit Precision Explained

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In Part 19, we explore the Time and Realtime Data Types in Verilog HDL used for simulation and debugging.
These data types help designers measure simulation time, delays, and represent precise time values in hardware modeling.

📖 Topics Covered

Types of time data types: time and realtime

Difference between time and realtime

Syntax and declaration examples

Default size, sign, and value of each

Format specifiers used in display statements

Practical code demonstrations with expected outputs

📌 Key Points about Time

Default width: 64 bits

Default value: x (unknown)

Default sign: unsigned

Used to represent simulation time quantities

Format specifier: %0t

📌 Example Code: time data type

verilog
module time_datatype;
time end_time = 50;
initial begin
$display("end_time = %0t", end_time);
// Since time is unsigned (64-bit), signed form is not supported
// If treated as unsigned → large 64-bit equivalent value for -50
end
endmodule
📌 Key Points about Realtime

Default width: 64 bits

Default value: 0.0

Default sign: signed (floating point)

Used for fractional or high-resolution time representation

Format specifier: %0t or %f depending on use

📌 Example Code: realtime data type

verilog
module realtime_datatype;
realtime rtime = -50;
integer a = $bits(rtime);
initial begin
$display("rtime = %0d bits", a);
end
endmodule
📌 Output

text
rtime = 64 bits
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