Resistive RAM (memristor) Modeling and In-memory Computing using Majority Logic

This is a guest lecture in which I summarize my recent work on ReRAM modeling and in-memory computing. In the first part of the talk (~ 25 mins) I talk about ReRAM modeling -how to take the Stanford-PKU model and fit it to any ReRAM device. In the second half of the talk, I discuss how a majority gate can be implemented in a ReRAM array with minimal change to the peripheral circuitry. Computing is simplified to a sequence of memory READ and WRITE operations. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is
demonstrated how parallel-prefix adders can be implemented in memory in O(log(n)) latency. A 32-bit adder can be implemented in 26 cycles, which is one of the fastest in-memory adders reported so far.
For more details, see:
1. John Reuben and Stefan Pechmann, "Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, doi: 10.1109/TVLSI.2021.3068470.
2. John Reuben, Mehrdad Biglari and Dietmar Fey, "Incorporating Variability of Resistive RAM in Circuit Simulations Using the Stanford–PKU Model," in IEEE Transactions on Nanotechnology, vol. 19, pp. 508-518, 2020, doi: 10.1109/TNANO.2020.3004666.
3. John Reuben, Dietmar Fey and Christian Wenger, "A Modeling Methodology for Resistive RAM Based on Stanford-PKU Model With Extended Multilevel Capability," in IEEE Transactions on Nanotechnology, vol. 18, pp. 647-656, 2019, doi: 10.1109/TNANO.2019.2922838.