How to create a timer in VHDL

Learn how to create a real-time clock module in VHDL that outputs the time since startup in hours, minutes, and seconds.

The blog post for this video:
https://vhdlwhiz.com/create-timer/

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Update December 2021:
The IncrementWrap procedure shown in this video doesn't work in the latest version of ModelSim/QuestaSim. I have updated the downloadable and the blog post above, but I can't update the video.

Read more about the issue here:
https://vhdlwhiz.com/using-procedure/...
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Measuring time is done by counting clock cycles. If you know how long a clock period is, you can measure any amount of time simply by counting clock cycles.

If the clock frequency that the design is running at is 100 MHz, one second will have passed when we have counted 100 million clock periods. If we need to count minutes, we can make another counter which is incremented when 60 seconds have passed. And similarly, we can implement an hour counter which increments when 60 minutes have passed.

We can make as many cascading counters as we need to measure days, weeks, months, or years. It's really limited only by how many resources we have available in our FPGA.

It's a good idea to send the clock frequency to the module as a generic. The clock frequency can then be assigned using the generic map when the module is instantiated. This means that we can use the same module in multiple designs, regardless of which clock frequency it's running at.