Lab 06 Part 01 Clock Glitching (intro and Deep Flip-Flop DFF)

Modern digital hardware systems rely heavily on a clean, stable clock signal to ensure synchronous behavior.
When an attacker injects clock glitches, the sequential logic can be forced into:
Unintended state transitions
Skipped operations
Faulty computation results
Bypassing security checks

Clock glitching is one of the most powerful physical attacks on:
Smartcards
Secure microcontrollers
Cryptographic accelerators
Finite State Machines (FSMs)
Authentication and access control hardware

This lab explores how clock glitches affect simple digital circuits through simulation using Verilog/SystemVerilog.


2.1 What Is a Clock Glitch?
A clock glitch is an abnormal, short-duration pulse intentionally injected into the clock network. It creates an unexpected rising edge, causing flip-flops and sequential logic to capture values prematurely.
Types of Clock Faults
Extra rising edge (Most common attack)
Shortened clock period
Double clocking
Asynchronous edge insertion



2.2 Why Clock Glitching Works

All synchronous circuits assume:
The clock period is stable
Only one rising edge occurs per cycle
Setup/hold times are respected

A glitch can violate these assumptions, leading to:
Wrong output values
Skipped states in FSM
Corrupted counters
Faulty encryption rounds

These effects are the basis of fault injection attacks, widely used in:
AES differential fault analysis (DFA)
Bypassing PIN verifications
Tampering microcontrollers
Breaking secure ICs



2.3 What We Simulate in This Lab

We simulate glitch attacks on the following modules:
D Flip-Flop (DFF)
4-bit Synchronous Counter
Finite State Machine (FSM)
AES AddRoundKey Stub (AES-like module)

Each experiment shows both:
Golden behavior → normal clock
Glitch behavior → faulty results

Students will observe how a single glitch:
changes timing
breaks sequential consistency
causes security vulnerabilities