RISC-V Processor Verification Case Study

Presented at DVCon U.S. 2021

The open RISC-V instruction set architecture is gaining traction with both semiconductor vendors and systems companies. But how to verify the RISC-V processor implementation, especially when developing the RTL and/or adding custom instructions? The goal of this presentation is to report on the techniques used and lessons learned for the verification of a RV64IMACBNSU RISC-V processor by an experienced SoC design team, including the development of the reference model and the SystemVerilog and C encapsulation of the reference model, the step-and-compare flow used included co-debug, and the Specman environment.

By:
Adi Maymon, NVIDIA
Shay Harari, NVIDIA
Lee Moore, Imperas Software Ltd
Larry Lapides, Imperas Software Ltd

https://dvcon.org
https://dvcon-proceedings.org