Logic Gates Simulation in VHDL | Quartus Lite & Vivado
Автор: The Computer Engineering Notebook
Загружено: 2026-01-01
Просмотров: 15
In this video, I show how to simulate basic logic gates (AND, OR, NAND, NOT) using a complete FPGA-style workflow with real industry tools.
We start by building logic gate schematics in Quartus Lite, then generate:
• VHDL design file (.vhd)
• VHDL testbench file (.vhd)
After that, we import the VHDL files into Vivado and run a behavioral simulation to view and analyze the results using waveforms.
⏱️ Chapters:
00:00 Introduction
00:36 Create New Project in Quartus
02:10 Create New Block Diagram / Schematic File
02:30 Creating Logic Gate Schematics
07:10 Generating VHDL Design File
09:25 Generating VHDL Testbench
11:20 Adding A, B Input Vectors to Testbench (00, 01, 10, 11)
13:50 Vivado – Create New Project
15:00 Import VHDL Files into Vivado
15:50 Run Simulation in Vivado
16:15 Viewing and Analyzing Waveforms
If this video helped you understand VHDL simulation and FPGA tools, please like the video, subscribe to the channel, and share it with others learning digital design.
#VHDL #Quartus #Vivado #FPGA
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