RTL2GDS Demo Part 2.2: Synthesis with Genus

Digital VLSI Design - Hands on Demonstration

This is part 2 of a series of demonstrations for carrying out an RTL2GDS ASIC Digital Implementation Flow. In this series, I cover the entire flow, starting with simulation and direct test of an RTL block, through synthesis, floorplanning, placement and routing. The flow is demonstrated on a small toy counter block that I showed in my Digital VLSI Design (DVD) lecture series and goes through all steps of the digital design flow. In this series, we use Cadence tools: Xcelium, Genus, Innovus, Voltus and Tempus and work according to the methodology that I developed for the EnICS Labs at Bar-Ilan University.

In this demo, I run a full synthesis flow on a small RTL block using the methodology that I introduced in the preface to this series (   • RTL2GDS Demo Part 1: Logic Simulation with...  ) using Cadence Genus. The demonstration covers all stages of synthesis from defining the environment (setting up variables), through design initiation (based on an MMMC flow), elaboration, synthesis, reporting and exporting the design.

In the first half of the demo (   • RTL2GDS Demo Part 2.1: Synthesis with Genus  ), I covered the first stages of setting up the design in Genus until Elaboration. At this point, our design is elaborated and inside the Genus database. This is the second half of the demo, starting with a bit about navigating the design and the database with collections and two port objects, then continuing on to the init_design command, that processes the MMMC and SDC, and so we will go over the SDC a bit. After that we can go on and synthesize our design and analyze the results.

The skeleton template of the scripts used in this tutorial can be found on the EnICS Labs github at https://github.com/enics-labs/rtl2gds...
Feel free to clone the repo and send comments and suggestions for improvement.

The entire DVD course can be accessed at https://enicslabs.com/academic-course...
You can find slide decks and links to all of my lectures on the EnICS Labs website at https://enicslabs.com/education/ or directly access my recordings through my YouTube channel @aditeman

Note that I have made significant effort to blur and block any and every reference of external IP, beyond the basic features of the EDA tools and open source projects. If you notice any piece of information that is not blocked, please inform me at [email protected] and I will correct this as soon as possible.



All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University