4. The Differences Between ASIC and FPGA RTL Coding

• 𝗥𝗲𝘀𝗲𝘁
ASIC: Standard cell library contains both asynchronous and synchronous reset flip-flops.
FPGA: Maybe have only one type of flip-flops (Both Xilinx and Altera recommends synchronous reset). Synthesis tools utilize extra logic to map the unsupported flip-flop type.

• 𝗣𝗼𝘄𝗲𝗿 𝘂𝗽 𝘀𝘁𝗮𝘁𝗲
ASIC: Not supported.
FPGA: Flip-flops can power up with a predefined state.

• 𝗩𝗲𝗰𝘁𝗼𝗿 𝘀𝗶𝘇𝗲
ASIC: Less constraints.
FPGA: Limited by the number of configurable blocks and interconnection routing.

• 𝗖𝗹𝗼𝗰𝗸𝗶𝗻𝗴
ASIC: Multi-phase and gated clocks are common for reducing power consumption.
FPGA: Prefer single global clock with enable signals; avoid gated clocks.

• 𝗠𝗲𝗺𝗼𝗿𝗶𝗲𝘀
ASIC: Custom memory blocks. May have different memory structure than FPGA.
FPGA: Use built-in block RAMs and distributed RAMs.

• 𝗗𝗲𝘀𝗶𝗴𝗻 𝗳𝗼𝗿 𝗧𝗲𝘀𝘁𝗮𝗯𝗶𝗹𝗶𝘁𝘆 (𝗗𝗙𝗧)
ASIC: Extensive DFT structures (Scan Chains, Built-In Self-Test (BIST)).
FPGA: Minimal DFT, as testing is less critical and reconfiguration allows for easy debugging.

#ASICvsFPGA #RTLcoding #HardwareDesign #DigitalDesign #VLSIdesign #ASIC #FPGA #ResetDesign #PowerUpState #VectorSize #ClockingStrategies #GatedClocks #MultiPhaseClocks #MemoryArchitecture #BlockRAM #DistributedRAM #DesignForTestability #DFT #ScanChains #BIST #Xilinx #Altera