VHDL FIR lowpass high pass filter: Vivado simulation and implementation

FIR filters in VHDL with detailed explanations of both low-pass and high-pass implementations on Pynq-Z2. Learn how to develop efficient parallel FIR filters with constant coefficients using tapped delay lines, multipliers, and pipelined adders.
The tutorial covers:
• Complete explanation of FIR filter architecture and mathematical foundations
• Step-by-step VHDL implementation with 32 taps and 11-bit coefficients
• Coefficient generation using MATLAB/Python with quantization techniques
• Vivado simulation setup with DDS compilers for testing both filter types
• Hardware implementation on FPGA evaluation boards (including Pynq-Z2)
• Practical debugging with Integrated Logic Analyzer (ILA)
You can find the VHDL code and Matlab file in following GitHub repository:
https://github.com/FPGAPS/VHDL_FIR_Fi...

Timeline:
00:00 Introduction to parallel FIR filter
02:15 MATLAB-based quantized filter tap generation
03:17 FIR Filter with DDS complier Vivado Simulation
05:11 Analyzing simulation waveforms
05:43 MATLAB configuration for high-pass coefficients
06:14 High-pass filter simulation results
06:23 VHDL FIR Filter Vivado implementation
06:51 Pynq-Z2 external clock for standalone PL operation
07:55 Clock pin configuration based on Pynq-Z2 board
08:18 Run bitstream and hardware verification