CMOS Inverter Layout Design with DRC and LVS using Pegasus in Cadence Virtuoso IC 23 (gpdk045)

Welcome to TronicWorks Tech!
In this tutorial, we move from schematic to layout design in Cadence Virtuoso IC 23, using the gpdk045 technology library. You’ll learn how to draw a CMOS layout, run Design Rule Check (DRC), and perform Layout Versus Schematic (LVS) verification using Pegasus.

This experiment bridges the gap between circuit design and physical implementation—an essential step in modern VLSI design flow.

🔑 What you’ll learn
1. Creating CMOS layout in Virtuoso Layout Editor
2. Setting up gpdk045 technology library
3. Running DRC in Pegasus and resolving layout violations
4. Performing LVS to verify schematic–layout consistency
5. Understanding layout layers and design rules
6. Tips for clean DRC & LVS passes in CMOS layouts

📂 Playlist: Cadence Virtuoso Lab Experiments

👉 Part of our “Learn Cadence from Basics” series covering transistor-to-layout CMOS VLSI design.

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Note: This tutorial is recorded using the Cadence Virtuoso IC 23 software, licensed under Dayananda Sagar University.

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