Serial Adder using Moore FSM | Verilog RTL Design & Testbench Explained

In this video, we’ll design and simulate a Serial Adder using the Moore Finite State Machine (FSM) model in Verilog HDL. You’ll learn how to implement a bit-by-bit addition of two binary numbers using sequential logic and understand the concept of FSM-based data processing in digital circuits.

💡 What You’ll Learn:
✅ Working principle of Serial Adder using Moore Model
✅ Step-by-step Verilog RTL coding and FSM design
✅ Testbench creation for waveform verification
✅ Simulation results and output waveform explanation

🧠 Key Concepts Covered:

Moore State Machine Overview

State Transition Diagram

Bit-by-Bit Addition using Flip-Flops and FSM

Synchronous Reset and Clock-driven Operation

📘 Code Files:
👉 Verilog RTL and Testbench codes are shown and explained in the video.
(You can add your GitHub or Google Drive link here if you want to share the files.)

🎯 Perfect for:

VLSI Students & Enthusiasts

RTL Designers & FPGA Beginners

Anyone learning FSM-based digital system design

📺 Watch till the end to understand how Moore FSM logic ensures stable and predictable output in sequential circuits.

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