8259 | Interrupt Controller | Basic Concepts | Assignment | MCQs with Explanations | Microprocessors

NPTEL Microprocessors and Interfacing Assignment 10

1. If the ICW1 of 8259A is initialized with 03H, which of the following statement is correct?
ICW4 is needed and operates in single mode
ICW4 is not needed and operates in single mode
ICW4 is needed and operates in cascaded mode
ICW4 is not needed and operates in cascaded mode
Ans: ICW4 is needed and operates in single mode
2. In fully nested mode of 8259A, if IR4 is assigned highest priority, then
IR3 have lowest priority
IR5 have lowest priority
IR0 have lowest priority
IR7 have lowest priority
Ans: IR3 have lowest priority
3. Which of the following is used in cascading mode of 8259A
ICW 1
ICW 2
ICW 3
ICW 4
Ans: ICW 3
4. If the port address of the 8259A for ICW 2 is 83H, then the port address of ICW 3 would be
80H
81H
82H
83H
Ans: 83H
5. If the chip select of 8259A is generated using CS=A7A6A5A4A3A2A1, then the port address of operation command word OCW 2 would be
48H
49H
B6H
B7H
Ans: B6H
6. For a call address interval of 4, which of the following control word need to be loaded into ICW 1 of 8259A?
03H
04H
08H
0AH
Ans: 04H
7. If 11H is loaded into OCW 1 of 8259A, then
IR7 and IR3 are masked
IR0 and IR4 are unmasked
IR0 and IR4 are masked
IR7 and IR3 are unmasked
Ans: IR0 and IR4 are masked

8. The maximum number of interrupts can be received by 8259A in cascaded mode are
8
16
32
64
Ans: 64