Webinar Introduction - Mapping SysML to Hardware Architecture

Mirabilis Design will be hosting a webinar session on “Mapping SysML to hardware architecture” on March 21st. More details on the time are provided in the links below.
Asia/Europe: https://us06web.zoom.us/meeting/regis...
Americas: https://us06web.zoom.us/meeting/regis...


In this webinar session, we will show how an existing SysML models, for example, the signal processing behavior task graph of a RADAR system, can be partitioned, distributed and mapped on a hardware architecture to determine the compute, communication and storage requirements. Using this approach designers can get detailed insight into the requirements and constraints for implementation, debugging and testing. The Radar example is mapped to a multi-board DSP module using the system-level modelling IP in VisualSim Architect.


The SysML use-case, parameters and requirements are mapped as graphical task graphs in VisualSim and each function is mapped to a hardware entity on the architecture. The hardware architecture can be a combination of multi-core, DSP, GPU, AI accelerators, memories, cache, interconnects and DMA. Each component can be configured independently, and a parameter sweep will be performed to identify the best configuration for the target performance and power requirements. Examples of reports generated can be efficiency, latency, throughput, buffer usage, power consumed, reliability and response to failures. These reports can be used to determine the clock speeds, power vs performance tradeoffs, memory types, bus and interconnect standards, and battery size.

SysML model is the common specification language that binds the entire design flow. The mapped model is leveraged for testing software functionality, debugging for vulnerability, cyber security and system test.

So, register now to join us and learn more about "Mapping SysML to Hardware Architecture" using the links below.
Asia/Europe: https://us06web.zoom.us/meeting/regis...
Americas: https://us06web.zoom.us/meeting/regis...