Why NOT DFE-Only?
The Path to 200Gbps Serial Links
Why TXFFE?
Почему CTLE?
How DSP is Killing the Analog in SerDes
Восстановление и синхронизация часов
Сжатие импульсов: как согласованная фильтрация усиливает слабые сигналы и повышает разрешение
What is clock and data recovery?
What is a SerDes and why do I need one?
Deep-Dive: 112Gbps 16nm CMOS TIA with Co-Packaged Photodiodes
Understanding Signal Integrity
Why Phase Noise Contributors in a PLL?
Why Equalization?
SERDES Clocking and Equalization for High-Speed Serial Links, Jack Kenney
Learn SDR 18: Symbol Timing Recovery with Symbol Sync
PLL's - Digital phase detectors
Why TX Driver in a SerDes?
Mueller and Muller Clock Synchronization Algorithm
ES3-3- "ADC-based Wireline Transceivers" - Yohan Frans
Почему НЕ только CTLE?