Using Vivado Clocking Wizard to generate different clock frequencies, MMCM & clock buffer explained

This video demonstrates clock management techniques on the Xilinx ZCU104 FPGA board, focusing on the Programmable Logic (PL) Fabric while bringing the clock form carrier card.

Using the Clocking Wizard IP to generate two different clock frequencies (100MHz and 200MHz) from a 300MHz input clock
Implementing a practical application that blinks two PL LEDs at different frequencies to demonstrate clock functionality
Exploring the ZCU104's various clock sources, including system clocks, programmable clocks, and user clocks based on schematic.
Detailed step-by-step guide for:

Creating a Vivado project
Configuring the Clocking Wizard IP
Setting up differential clock inputs
Implementing reset functionality using the CPU reset button
Pin assignments and bitstream generation

The tutorial also covers important concepts like Mixed-Mode Clock Manager (MMCM), clock buffer usage, and proper clock distribution techniques in FPGA design. It's ideal for FPGA developers looking to understand clock management and frequency synthesis in modern FPGA designs.