Vivado Implementation of Synchronous LED Shifter : Clocking Wizard + VHDL Module + I/O planning

What if we want to use only the Programmable Logic (PL) resources and run VHDL code to control some I/O ports? In this design, I intentionally avoided using the Processing System (Zynq UltraScale+ IP) block. This approach emphasizes utilizing an external clock source instead of relying on the clocks provided by the PS. Additionally, this example demonstrates the proper implementation of a synchronous reset in the design.
This tutorial covers VHDL implementation, clock management, synchronized reset handling, and proper I/O planning. We demonstrate practical hardware integration while focusing exclusively on programmable logic capabilities.
Key Learning Outcomes:

VHDL module implementation for LED control
Integration of VHDL code in IP block design
I/O planning : ZCU104 carrier card resource utilization
Clock management using Clocking Wizard
Synchronized reset implementation with Processor System Reset IP

key topics:
00:00 Block Diagram Overview
02:53 VHDL Code Review
05:34 Vivado Project Setup
05:49 Clocking Wizard with differential input
06:43 VHDL Module Integration
09:21 I/O Planning and Pin Assignment
10:44 Hardware Implementation

You can download the VHDL code and constraint file from our GitHub:
https://github.com/FPGAPS/ZCU104_LED_...