Automating the design of bespoke AI accelerators for FPGAs

Automating the design of bespoke AI accelerators for FPGAs
At the limits of power, performance and area, Edge AI's demand for low-latency, energy-efficient hardware challenges traditional inference capabilities. Whether it is Object Detection, Image Segmentation or Super Resolution, edge devices each have unique requirements and constraints for the application they are deploying. GPUs and NPUs struggle with inefficiencies in any particular one due to their generalized "one-size-fits-all" design approach. On the other hand, the versatility of FPGAs allow for highly specialized and therefore efficient hardware designs. To realize the potential of FPGAs for AI applications, Heronic has created a toolflow for designing bespoke AI accelerators for FPGA systems. This talk will cover how engineers can leverage the benefits of Heronic’s approach to accelerator design for FPGA devices.