Validate and Implement a RISC-V core using AI

Validate and Implement a RISC-V core using AI
This project validated and implemented a RISC-V core using AI, focusing on distinct verification and implementation phases. Verification aimed to explore verification flow and conduct coverage analysis of a Bluespec MCU SoC. The implementation phase involved creating a baseline RISC-V core design using Synopsys Fusion Compiler™, which was subsequently optimized for Power, Performance, and Area (PPA) with Synopsys DSO.ai™ by exploring search space with custom permutons. This resulted in 2 separate designs; one running at a 500MHz frequency with power and area significantly under target PPA requirements, and another running at 1GHz with higher power and area metrics while still conforming to target PPA requirements.