Verification IP – Trends and Technology for FPGA and ASIC Design Verification

Speaker: Adam Rose

Abstract:
This session will introduce and discuss new EZ-VIP for PCI Express that provides re-usable building blocks for common protocols and architectures for reduced testbench assembly time for FPGA design verification.
-Why FPGA designers need verification IP for complex protocols such as PCIe
-What do FPGA designers need from PCIe VIP and how does this differ from ASIC verification?
-What is Mentor’s EZ-VIP and how to get started
-Partnerships with PCIe design IP suppliers and usage examples and successes