SystemVerilog Assertions From Scratch | Crack VLSI Interview

SystemVerilog Assertions
Assertions are used to check design rules or specifications and generate warnings or errors in case of assertion failures. An assertion also provides function coverage that makes sure a certain design specification is covered in the verification. The methodology that uses assertions is commonly known as “Assertion Based Verification” (ABV). Assertions can be written in the design as well as the verification environment.

Advantages of using Assertions
Checks design specifications and reports errors or warnings in case of failure.
It improves debugging time. For example, a bug due to an illegal state transition can propagate to the output. Writing an assertion helps out to improve debugging time.
Can be used in formal verification.
Can be re-used across verification testbench or design.
Can be parameterized
Can be turned on/off based on the requirement.
Types of Assertions
Immediate assertions
Concurrent assertions


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