VLSI Physical Design Verification Deep Dive : The Complete Marathon

In this video, we delve into a comprehensive series of essential topics in Physical Design (PD) Verification (PV or Phy-Ver) for VLSI. We begin by exploring the importance of Physical Design and then move on to foundational concepts like Process Design Kits (PDK) and Design Kits (DK). The video covers critical checks and analyses such as Design Rule Check (DRC), Layout Versus Schematic (LVS), and the role of interconnects and their delays in chip design. We also discuss advanced topics including on-chip inductance, decap cells, and Standard Parasitic Exchange Format (SPEF) files. Furthermore, the series concludes with an in-depth look at power integrity and reliability issues such as IR drop analysis, electromigration and its effects due to temperature, voltage, and frequency, ground bounce, crosstalk, antenna effects, and Electrostatic Discharge (ESD) protection in VLSI design.

Chapters:
00:00:00 Intro & Beginning
00:01:38 EP-01-Why-PD-important
00:17:05 EP-02-PDK-DK-In-VLSI
00:28:09 EP-03-Design Rule Check (DRC)
00:50:33 EP-04-Layout Vs Schematic (LVS)
01:04:04 EP-05-Interconnects-In-VLSI
01:35:37 EP-06-Interconnect-Delays-In-PD
02:00:02 EP-07-OnChip-Inductance
02:24:23 EP-08-What-Is-DECAP-Cell
02:40:26 EP-09-SPEF-File (Standard Parasitic Exchange Format) a.k.a PEX File
03:12:22 EP-10-1-IR-Drop-Analysis-VLSI
03:40:03 EP-10-2-EM (Electromigration)-Theory
03:56:52 EP-10-3-EM (Electromigration)-Temperature-Effect
04:14:03 EP-10-4-EM (Electromigration)-Voltage_Frequency-Effect
04:33:46 EP-10-5-Ground-Bounce
04:44:37 EP-11-Crosstalk
05:15:11 EP-12-Antenna-Effect-In-VLSI
05:35:18 EP-13-ESD-In-VLSI

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